<p>OT - Not that this is definitive, but one of my friends is well versed in most all things computer code related, so I though I'd share his reaction.   I sent him the Barron's article, and his take on it was this:</p> <p>"<span>At first blush, the technique seems to be dependent on knowledge of the hardware at each end of the encryption.  If so, that would limits its universality.</span></p> <p>Specifically, the technique would need to know the register configuration, details of the CPU fetch-execute cycles, and CPU microcode.  An Intel i7 chip would work one way with a matching i7 at the other end, but differently with an AMD Ryzen chip at the other end.  Both Intel and AMD have the ability to update the microcode in their chips at any time, so the firmware version would be important.  All of these chips run multiprocessor / multi-threaded with non-deterministic instruction look-ahead.  The logistics might be cumbersome, at best.  </p> <p>Also, the article describes pretty clearly what the technique is and, if it works, enables other people to implement something similar."</p>